Field-Programmable Gate Arrays (FPGAs) Simulator in Rust

Field-Programmable Gate Arrays (FPGAs) are integrated circuits designed to be configured by a customer or a designer after manufacturing. They are used in a wide range of applications due to their flexibility, parallel processing capabilities, and efficiency. 🦀

In this article, we’ll build a simple FPGA simulator in Rust, starting with basic logic gates and gradually adding more complexity. By the end, we’ll demonstrate how FPGAs can perform parallel processing.

Basic Implementation

We’ll start by defining a simple structure for an FPGA and implement basic logic gates: AND, OR, NOT, and XOR.

Step 1: Setting Up the Project

First, create a new Rust project using Cargo:

cargo new fpga_sim
cd fpga_sim

Step 2: Define Basic Gates

Create a new file src/gate.rs and add the following code:

pub enum GateType {
    And,
    Or,
    Not,
    Xor,
}

pub struct Gate {
    pub gate_type: GateType,
    pub inputs: Vec<bool>,
    pub output: bool,
}

impl Gate {
    pub fn new(gate_type: GateType, input_count: usize) -> Gate {
        Gate {
            gate_type,
            inputs: vec![false; input_count],
            output: false,
        }
    }

    pub fn process(&mut self) {
        match self.gate_type {
            GateType::And => {
                self.output = self.inputs.iter().all(|&x| x);
            }
            GateType::Or => {
                self.output = self.inputs.iter().any(|&x| x);
            }
            GateType::Not => {
                self.output = !self.inputs[0];
            }
            GateType::Xor => {
                self.output = self.inputs.iter().fold(false, |acc, &x| acc ^ x);
            }
        }
    }
}

pub struct Fpga {
    pub gates: Vec<Gate>,
}

impl Fpga {
    pub fn new() -> Fpga {
        Fpga {
            gates: Vec::new(),
        }
    }

    pub fn add_gate(&mut self, gate: Gate) -> usize {
        self.gates.push(gate);
        self.gates.len() - 1
    }

    pub fn set_input(&mut self, gate_index: usize, input_index: usize, value: bool) {
        self.gates[gate_index].inputs[input_index] = value;
    }

    pub fn process(&mut self) {
        for gate in &mut self.gates {
            gate.process();
        }
    }

    pub fn get_output(&self, gate_index: usize) -> bool {
        self.gates[gate_index].output
    }
}

Using the FPGA

Edit the src/main.rs file to use the FPGA module:

mod gate;

use gate::{Fpga, Gate, GateType};

fn main() {
    let mut my_fpga = Fpga::new();

    // Add gates
    let and_gate_index = my_fpga.add_gate(Gate::new(GateType::And, 2));
    let or_gate_index = my_fpga.add_gate(Gate::new(GateType::Or, 2));
    let not_gate_index = my_fpga.add_gate(Gate::new(GateType::Not, 1));
    let xor_gate_index = my_fpga.add_gate(Gate::new(GateType::Xor, 2));

    // Set inputs
    my_fpga.set_input(and_gate_index, 0, true);
    my_fpga.set_input(and_gate_index, 1, false);

    // Process FPGA
    my_fpga.process();

    // Get the output
    let and_result = my_fpga.get_output(and_gate_index);
    println!("FPGA AND gate result: {}", and_result);

    // Set inputs for OR gate
    my_fpga.set_input(or_gate_index, 0, true);
    my_fpga.set_input(or_gate_index, 1, false);

    // Process FPGA
    my_fpga.process();

    // Get the output
    let or_result = my_fpga.get_output(or_gate_index);
    println!("FPGA OR gate result: {}", or_result);
}

Run the project using Cargo:

cargo build
cargo run

Adding More Complexity

Now, we will add more complex gates, such as an adder for arithmetic operations, and implement a simple calculator.

Step 1: Add Adder Gate

Update src/gate.rs to include an adder gate:

pub enum GateType {
    And,
    Or,
    Not,
    Xor,
    Adder,
}

impl Gate {
    pub fn process(&mut self) {
        match self.gate_type {
            // Other gates...
            GateType::Adder => {
                let sum = self.inputs[0] as u8 + self.inputs[1] as u8;
                self.output = (sum % 2) == 1;
            }
        }
    }
}

Step 2: Update Main Program

Update src/main.rs to use the adder gate:

mod gate;

use gate::{Fpga, Gate, GateType};

fn main() {
    let mut my_fpga = Fpga::new();

    // Add gates
    let adder_gate_index = my_fpga.add_gate(Gate::new(GateType::Adder, 2));

    // Set inputs for adder
    my_fpga.set_input(adder_gate_index, 0, true);
    my_fpga.set_input(adder_gate_index, 1, false);

    // Process FPGA
    my_fpga.process();

    // Get the output
    let add_result = my_fpga.get_output(adder_gate_index);
    println!("FPGA ADD gate result: {}", add_result);
}

Implementing a Multi-Bit Adder

To handle multi-bit numbers, we need to create a ripple-carry adder:

Step 1: Update src/gate.rs

Add carry handling to the adder gate:

pub struct Gate {
    pub gate_type: GateType,
    pub inputs: Vec<bool>,
    pub output: bool,
    pub carry_out: Option<bool>,
}

impl Gate {
    pub fn new(gate_type: GateType, input_count: usize) -> Gate {
        Gate {
            gate_type,
            inputs: vec![false; input_count],
            output: false,
            carry_out: None,
        }
    }

    pub fn process(&mut self) {
        match self.gate_type {
            // Other gates...
            GateType::Adder => {
                let sum = self.inputs[0] as u8 + self.inputs[1] as u8 + self.inputs.get(2).copied().unwrap_or(false) as u8;
                self.output = (sum % 2) == 1;
                self.carry_out = Some((sum / 2) == 1);
            }
        }
    }
}

Step 2: Update Main Program for Multi-Bit Adder

Update src/main.rs to handle multi-bit addition:

mod gate;

use gate::{Fpga, Gate, GateType};
use std::io::{self, Write};

fn bool_to_bin_str(value: bool) -> &'static str {
    if value { "1" } else { "0" }
}

fn int_to_bool_vec(n: u8, bit_size: usize) -> Vec<bool> {
    (0..bit_size).rev().map(|i| (n & (1 << i)) != 0).collect()
}

fn bool_vec_to_int(bits: &[bool]) -> u8 {
    bits.iter().rev().enumerate().fold(0, |acc, (i, &b)| acc | ((b as u8) << i))
}

fn main() {
    let mut my_fpga = Fpga::new();
    let bit_size = 4;

    // Add gates for multi-bit adder
    let mut adders = vec![];
    for _ in 0..bit_size {
        adders.push(my_fpga.add_gate(Gate::new(GateType::Adder, 3)));
    }

    loop {
        println!("Simple FPGA Calculator");
        println!("1. ADD");
        println!("2. Exit");
        print!("Choose an operation: ");

        io::stdout().flush().unwrap();

        let mut choice = String::new();

        io::stdin().read_line(&mut choice).unwrap();

        let choice: u8 = match choice.trim().parse() {
            Ok(num) => num,
            Err(_) => continue,
        };

        if choice == 2 {
            break;
        }

        if choice != 1 {
            println!("Invalid choice, please choose 1 or 2.");
            continue;
        }

        print!("Enter the first operand (0-15): ");

    io::stdout().flush().unwrap();

    let mut operand1 = String::new();

    io::stdin().read_line(&mut operand1).unwrap();
    let operand1: u8 = match operand1.trim().parse() {
        Ok(num) if num < 16 => num,
        _ => continue,
    };
    print!("Enter the second operand (0-15): ");

    io::stdout().flush().unwrap();

    let mut operand2 = String::new();
    io::stdin().read_line(&mut operand2).unwrap();

    let operand2: u8 = match operand2.trim().parse() {
        Ok(num) if num < 16 => num,
        _ => continue,
    };
    let operand1_bits = int_to_bool_vec(operand1, bit_size);
    let operand2_bits = int_to_bool_vec(operand2, bit_size);

    for i in 0..bit_size {
        my_fpga.set_input(adders[i], 0, operand1_bits[i]);
        my_fpga.set_input(adders[i], 1, operand2_bits[i]);
        if i == 0 {
            my_fpga.set_input(adders[i], 2, false);
        } else {
            my_fpga.add_connection(adders[i - 1], adders[i], 2);
        }
    }
    my_fpga.process();

    let result_bits: Vec<bool> = adders.iter().map(|&index| my_fpga.get_output(index)).collect();
    let result = bool_vec_to_int(&result_bits);
    let carry_out = my_fpga.get_carry_out(adders[bit_size - 1]).unwrap();

    println!("ADD result: {} (carry out: {})", result, bool_to_bin_str(carry_out));
}

}

### Demonstrating Parallel Processing

To showcase the parallel processing capabilities of an FPGA, we will create a system that performs multiple multiplications simultaneously.

#### Step 1: Update `src/gate.rs`

Ensure the file includes a multiplier gate:

```rust
impl Gate {
    pub fn process(&mut self) {
        match self.gate_type {
            // Other gates...

            GateType::Multiplier => {
                let prod = self.inputs[0] as u8 * self.inputs[1] as u8;
                self.output = (prod % 2) == 1;
                self.carry_out = Some((prod / 2) == 1);
            }
        }
    }
}

Step 2: Implement Parallel Multiplication

Update src/main.rs to perform multiple multiplications in parallel:

mod gate;

use gate::{Fpga, Gate, GateType};
use std::io::{self, Write};

fn bool_to_bin_str(value: bool) -> &'static str {
    if value { "1" } else { "0" }

}

fn int_to_bool_vec(n: u8, bit_size: usize) -> Vec<bool> {
    (0..bit_size).rev().map(|i| (n & (1 << i)) != 0).collect()
}

fn bool_vec_to_int(bits: &[bool]) -> u8 {
    bits.iter().rev().enumerate().fold(0, |acc, (i, &b)| acc | ((b as u8) << i))
}

fn main() {
    let mut my_fpga = Fpga::new();
    let bit_size = 4;
    let mut multipliers = vec![];

    for _ in 0..4 {
        multipliers.push(my_fpga.add_gate(Gate::new(GateType::Multiplier, 2)));
    }

    loop {
        println!("Parallel FPGA Multiplier");
        println!("Enter pairs of numbers to multiply (0-15).");
        println!("You will enter 8 numbers to form 4 pairs.");
        println!("Example: 2 3 4 5 6 7 8 9");
        print!("Enter the numbers: ");

        io::stdout().flush().unwrap();

        let mut input = String::new();
        io::stdin().read_line(&mut input).unwrap();

        let numbers: Vec<u8> = input
            .split_whitespace()
            .filter_map(|s| s.parse().ok())
            .collect();

        if numbers.len() != 8 || numbers.iter().any(|&n| n > 15) {
            println!("Invalid input. Please enter 8 numbers between 0 and 15.");
            continue;
        }

        for i in 0..4 {
            let operand1_bits = int_to_bool_vec(numbers[2 * i], bit_size);
            let operand2_bits = int_to_bool_vec(numbers[2 * i + 1], bit_size);
            my_fpga.set_input(multipliers[i], 0, operand1_bits[bit_size - 1]);
            my_fpga.set_input(multipliers[i], 1, operand2_bits[bit_size - 1]);
        }

        my_fpga.process();

        for i in 0..4 {
            let result_bits: Vec<bool> = (0..bit_size)
                .map(|_| my_fpga.get_output(multipliers[i]))
                .collect();
            let result = bool_vec_to_int(&result_bits);
            println!("Result of pair {}: {}", i + 1, result);
        }
    }
}

Implementing variable bit size operations

To make the bit size variable instead of fixed at 4 bits, we need to adjust our FPGA simulator to handle operations on a variable number of bits. This involves modifying the input handling and gate processing to dynamically adapt to the specified bit size.

Step 1: Update the src/gate.rs to Handle Variable Bit Size

First, we’ll modify the Gate and Fpga structures to support a variable bit size.

pub enum GateType {
    And,
    Or,
    Not,
    Xor,
    Nand,
    Nor,
    Adder,
    Subtractor,
    Multiplier,
}

pub struct Gate {
    pub gate_type: GateType,
    pub inputs: Vec<bool>,
    pub output: bool,
    pub carry_out: Option<bool>,
}

impl Gate {
    pub fn new(gate_type: GateType, input_count: usize) -> Gate {
        Gate {
            gate_type,
            inputs: vec![false; input_count],
            output: false,
            carry_out: None,
        }
    }

    pub fn process(&mut self) {
        match self.gate_type {
            GateType::And => {
                self.output = self.inputs.iter().all(|&x| x);
            }
            GateType::Or => {
                self.output = self.inputs.iter().any(|&x| x);
            }
            GateType::Not => {
                self.output = !self.inputs[0];
            }
            GateType::Xor => {
                self.output = self.inputs.iter().fold(false, |acc, &x| acc ^ x);
            }
            GateType::Nand => {
                self.output = !(self.inputs.iter().all(|&x| x));
            }
            GateType::Nor => {
                self.output = !(self.inputs.iter().any(|&x| x));
            }
            GateType::Adder => {
                let sum = self.inputs[0] as u8 + self.inputs[1] as u8 + self.inputs.get(2).copied().unwrap_or(false) as u8;
                self.output = (sum % 2) == 1;
                self.carry_out = Some((sum / 2) == 1);
            }
            GateType::Subtractor => {
                let diff = self.inputs[0] as i8 - self.inputs[1] as i8;
                self.output = (diff % 2) != 0;
                self.carry_out = Some((diff < 0));
            }
            GateType::Multiplier => {
                let prod = self.inputs[0] as u8 * self.inputs[1] as u8;
                self.output = (prod % 2) == 1;
                self.carry_out = Some((prod / 2) == 1);
            }
        }
    }
}

pub struct Fpga {
    pub gates: Vec<Gate>,
    pub connections: Vec<(usize, usize, usize)>, // (output_gate_index, input_gate_index, input_index)
    pub bit_size: usize,
}

impl Fpga {
    pub fn new(bit_size: usize) -> Fpga {
        Fpga {
            gates: Vec::new(),
            connections: Vec::new(),
            bit_size,
        }
    }

    pub fn add_gate(&mut self, gate: Gate) -> usize {
        self.gates.push(gate);
        self.gates.len() - 1
    }

    pub fn add_connection(&mut self, output_gate: usize, input_gate: usize, input_index: usize) {
        self.connections.push((output_gate, input_gate, input_index));
    }

    pub fn set_input(&mut self, gate_index: usize, input_index: usize, value: bool) {
        self.gates[gate_index].inputs[input_index] = value;
    }

    pub fn process(&mut self) {
        for gate in &mut self.gates {
            gate.process();
        }
        let mut updated = true;
        while updated {
            updated = false;
            for (output_gate, input_gate, input_index) in &self.connections {
                let output_value = self.gates[*output_gate].output;
                if self.gates[*input_gate].inputs[*input_index] != output_value {
                    self.gates[*input_gate].inputs[*input_index] = output_value;
                    updated = true;
                }
            }
            for gate in &mut self.gates {
                gate.process();
            }
        }
    }

    pub fn get_output(&self, gate_index: usize) -> bool {
        self.gates[gate_index].output
    }

    pub fn get_carry_out(&self, gate_index: usize) -> Option<bool> {
        self.gates[gate_index].carry_out
    }
}

Step 2: Update the Main Program to Handle Variable Bit Size

Next, we’ll modify the main program to accept a variable bit size and perform multi-bit addition.

mod gate;

use gate::{Fpga, Gate, GateType};
use std::io::{self, Write};

fn bool_to_bin_str(value: bool) -> &'static str {
    if value { "1" } else { "0" }
}

fn int_to_bool_vec(n: u32, bit_size: usize) -> Vec<bool> {
    (0..bit_size).rev().map(|i| (n & (1 << i)) != 0).collect()
}

fn bool_vec_to_int(bits: &[bool]) -> u32 {
    bits.iter().rev().enumerate().fold(0, |acc, (i, &b)| acc | ((b as u32) << i))
}

fn main() {
    print!("Enter the bit size: ");
    io::stdout().flush().unwrap();

    let mut bit_size_input = String::new();

    io::stdin().read_line(&mut bit_size_input).unwrap();
    let bit_size: usize = bit_size_input.trim().parse().expect("Invalid bit size");
    let mut my_fpga = Fpga::new(bit_size);

    // Add gates for multi-bit adder
    let mut adders = vec![];
    for _ in 0..bit_size {
        adders.push(my_fpga.add_gate(Gate::new(GateType::Adder, 3)));
    }
    loop {
        println!("Simple FPGA Calculator");
        println!("1. ADD");
        println!("2. Exit");
        print!("Choose an operation: ");

        io::stdout().flush().unwrap();
        let mut choice = String::new();
        io::stdin().read_line(&mut choice).unwrap();
        let choice: u8 = match choice.trim().parse() {
            Ok(num) => num,
            Err(_) => continue,
        };
        if choice == 2 {
            break;
        }
        if choice != 1 {
            println!("Invalid choice, please choose 1 or 2.");
            continue;
        }
        let max_value = (1 << bit_size) - 1;
        print!("Enter the first operand (0-{}): ", max_value);
        io::stdout().flush().unwrap();
        let mut operand1 = String::new();

        io::stdin().read_line(&mut operand1).unwrap();

        let operand1: u32 = match operand1.trim().parse() {
            Ok(num) if num <= max_value => num,
            _ => continue,
        };

        print!("Enter the second operand (0-{}): ", max_value);

        io::stdout().flush().unwrap();

        let mut operand2 = String::new();

        io::stdin().read_line(&mut operand2).unwrap();
        let operand2: u32 = match operand2.trim().parse() {
            Ok(num) if num <= max_value => num,
            _ => continue,
        };
        let operand1_bits = int_to_bool_vec(operand1, bit_size);
        let operand2_bits = int_to_bool_vec(operand2, bit_size);

        for i in 0..bit_size {
            my_fpga.set_input(adders[i], 0, operand1_bits[i]);
            my_fpga.set_input(adders[i], 1, operand2_bits[i]);
            if i == 0 {
                my_fpga.set_input(adders[i], 2, false);
            } else {
                my_fpga.add_connection(adders[i - 1], adders[i], 2);
            }
        }

        my_fpga.process();

        let result_bits: Vec<bool> = adders.iter().map(|&index| my_fpga.get_output(index)).collect();
        let result = bool_vec_to_int(&result_bits);
        let carry_out = my_fpga.get_carry_out(adders[bit_size - 1]).unwrap();

        println!("ADD result: {} (carry out: {})", result, bool_to_bin_str(carry_out));
    }
}

In this article, we built a simple FPGA simulator in Rust, starting with basic logic gates and gradually adding more complexity. We demonstrated how to implement a multi-bit adder and showcased the parallel processing capabilities of an FPGA by performing multiple multiplications simultaneously.